Support AMD threshold vector APIC setup on 32bit Needed for the 64bit machine check code. Signed-off-by: Andi Kleen --- arch/x86/kernel/apic_32.c | 24 ++++++++++++++++++++++++ include/asm-x86/mach-default/irq_vectors.h | 3 ++- 2 files changed, 26 insertions(+), 1 deletion(-) Index: linux/include/asm-x86/mach-default/irq_vectors.h =================================================================== --- linux.orig/include/asm-x86/mach-default/irq_vectors.h +++ linux/include/asm-x86/mach-default/irq_vectors.h @@ -41,13 +41,14 @@ * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. * TLB, reschedule and local APIC vectors are performance-critical. * - * Vectors 0xf0-0xfa are free (reserved for future Linux use). + * Vectors 0xf0-0xf9 are free (reserved for future Linux use). */ #define SPURIOUS_APIC_VECTOR 0xff #define ERROR_APIC_VECTOR 0xfe #define INVALIDATE_TLB_VECTOR 0xfd #define RESCHEDULE_VECTOR 0xfc #define CALL_FUNCTION_VECTOR 0xfb +#define THRESHOLD_APIC_VECTOR 0xfa #define THERMAL_APIC_VECTOR 0xf0 /* Index: linux/arch/x86/kernel/apic_32.c =================================================================== --- linux.orig/arch/x86/kernel/apic_32.c +++ linux/arch/x86/kernel/apic_32.c @@ -226,6 +226,30 @@ static void __setup_APIC_LVTT(unsigned i } /* + * Setup extended LVT, AMD specific (K8, family 10h) + * + * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and + * MCE interrupts are supported. Thus MCE offset must be set to 0. + */ + +#define APIC_EILVT_LVTOFF_MCE 0 +#define APIC_EILVT_LVTOFF_IBS 1 + +static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) +{ + unsigned long reg = (lvt_off << 4) + APIC_EILVT0; + unsigned int v = (mask << 16) | (msg_type << 8) | vector; + + apic_write(reg, v); +} + +u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) +{ + setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); + return APIC_EILVT_LVTOFF_MCE; +} + +/* * Program the next event, relative to now */ static int lapic_next_event(unsigned long delta,